I am reading some pieces of Linux kernel code and find some concepts
about cold cache and warm cache, they are new to me, google didn't
help me much, so what are they? Can anyone explain them for me?

TIA.
ABAI

"Bin Chen" <binary.chen> writes:

> I am reading some pieces of Linux kernel code and find some concepts
> about cold cache and warm cache, they are new to me, google didn't
> help me much, so what are they? Can anyone explain them for me?
>
Emm, they are interesting, and I have never heard them before either.

I got this url from google,
http://blog.ftwr.co.uk/wordpress/wp-cache-inspect/

Cold Cache Hits
This is the number of cached items that were loaded from disk.

Warm Cache Hits
This is the number of cached items accessed that were already in
memory.

I am not sure they are what you want. Hope they are useful.

On Mar 11, 7:38 pm, Yao Qi <qiyao> wrote:
> "Bin Chen" <binaryc> writes:
>
> Emm, they are interesting, and I have never heard them before either.
>
> I got this url from google,[..]
>
> Cold Cache Hits
> This is the number of cached items that were loaded from disk.
>
> Warm Cache Hits
> This is the number of cached items accessed that were already in
> memory.
>
> I am not sure they are what you want. Hope they are useful.
>
Thanks. This is the meaning in 'wordpress' context, but I want the
meaning in the CS context... :) Maybe there are some connections
among, but I prefer more formal definition.

"Bin Chen" <binary.chen> writes:

> I am reading some pieces of Linux kernel code and find some concepts
> about cold cache and warm cache, they are new to me, google didn't
> help me much, so what are they? Can anyone explain them for me?

A cache in general is a fast temporary store that speeds up access to
a (larger) slower store.

Compared to the frequency of your CPU your RAM chips are very very
slow. A modern CPU has caches to improve memory performance when
accessing memory. It holds frequently used data in its caches.

In fact most of the transistors on a x86 CPU tend to serve as cache these days.

Cache cold is data that isn't in the CPU's cache and takes longer to access,
cache hot is data that is in cache.

http://www.halobates.de/memory.pdf slide 4 has a overview over the performance
ratios involved. In general memory access (= cache misses) on a modern system
are very very slow compared to the performance the CPU can reach when
it works on cached data. This is why in algorithm design for modern CPUs
it is now often more important to save memory (or access memory efficiently)
instead of finding the best algorithm.

The concept applies to all kinds of other caches (disk caches, ...) too of course.

-Andi

Andi Kleen <freitag> writes:


> A cache in general is a fast temporary store that speeds up access to
> a (larger) slower store.
>
> Compared to the frequency of your CPU your RAM chips are very very
> slow. A modern CPU has caches to improve memory performance when
> accessing memory. It holds frequently used data in its caches.

Good explanations on cache!

>
> In fact most of the transistors on a x86 CPU tend to serve as cache
> these days.

Why do you say this? x86 is a CISC architecture, with limited
registers. Why *most* of the transistors on x86 CPU tend to server as
cache?

>
> Cache cold is data that isn't in the CPU's cache and takes longer to
> access,
> cache hot is data that is in cache.
>

The more memory accesses to a address hit on a cache, the hotter of this
cache, associated to this address.

If we write a program, in which most of memory accesses are done in
cache, we could say this program is cache-hot; otherwise, cache miss
rate is very high, this program is cache-cold.

Correct me, if I am wrong. Thanks!

Yao Qi <qiyaoltc> writes:

> > In fact most of the transistors on a x86 CPU tend to serve as cache
> > these days.
>
> Why do you say this? x86 is a CISC architecture, with limited
> registers. Why *most* of the transistors on x86 CPU tend to server as
> cache?

This has nothing to do with CISC or registers. It's just how modern
CPUs are designed. Cache is relatively easy to design and uses
less power than logic and the more cache available the better the performance
So it's an easy choice for the CPU designer.
>
> If we write a program, in which most of memory accesses are done in
> cache, we could say this program is cache-hot; otherwise, cache miss
> rate is very high, this program is cache-cold.

"Cache cold" and "cache hot" doesn't refer to whole caches or to programs,
but to small pieces of caches. They are called cache lines because
that is the smallest unit a CPU cache can store data. They are normally
between 32 and 128 bytes depending on the CPU.

So you normally say a piece of data (or code) is cache hot or cold.

-Andi

"Bin Chen" <binary.chen> writes:

> I am reading some pieces of Linux kernel code and find some concepts
> about cold cache and warm cache, they are new to me, google didn't
> help me much, so what are they? Can anyone explain them for me?

Recommended reading: "UNIX Systems for Modern Architectures", Curt
Schimmel.

/holger

In article <m31wjscefl.fsf>, Yao Qi <qiyaoltc> wrote:

>Why do you say this? x86 is a CISC architecture, with limited
>registers. Why *most* of the transistors on x86 CPU tend to server as
>cache?

Because the chip has a cache on it and he's saying that that cache
is responsible for most of the transistor count.

ellis wrote:

> In article <m31wjscefl.fsf>, Yao Qi <qiyaoltc> wrote:
>
>>Why do you say this? x86 is a CISC architecture, with limited
>>registers. Why *most* of the transistors on x86 CPU tend to server as
>>cache?
>
> Because the chip has a cache on it and he's saying that that cache
> is responsible for most of the transistor count.

And for some X86 processors this is true. Here is the die photograph
of an dual-core Opteron:

http://images.sudhian.com/review/cpu...5/Dualcore.jpg

The large regular area on the left is the unified 1 MByte L2 cache.
On the right you see the two identical processor cores.

Each of those has two (Instruction + data) L1 cache blocks of 64KB each.

To get transistor counts, you have to account for higher transistor
density of the cache compared to gate logic.

Kind regards,

Iwo